State of the art processor systems, esp. in embedded systems, are not able resp. foreseen to process data under real-time conditions especially with throughput rates near 10 Gbps. So, when using interfaces like PCI Express (PCIe) or Infiniband or 10G-Ethernet under real-time conditions for 10 Gbps data throughput, special data-paths have to process the high throughput rate data. But tasks like connection management or time uncritical control messaging are better manageable by a processor.
A problem is that the data packets for the real time data transfer and the bus management and/or other control messages occur intermixed on the PCIe bus. When completions need to be generated for the real-time data transfer a problem may occur that the other messages will not led through the interface fast enough.
Invention
To solve the problem, the invention proposes a kind of multiplexer architecture to split between control and data-path accesses for high bandwidth interface architectures.
A packet oriented control scheme for accessing a high bandwidth interface core such as PCIe core, for connection management purpose is separated from a packet oriented data processing scheme by an intelligent multiplexer/FIFO control architecture. This multiplexer supports a priority scheme and e.g. PCIe aligned packet length while switching.
An advantage of the invention is that it significantly saves processor performance by distinguishing between data-path and control-path in high bandwidth interface based architectures.
The invention provides for a maximum data throughput.